PROJECT 02 / MODEL ARCHITECTURE

EILER.

A sequence model must decide
what to carry forward.

EILER (Eigen-Integrated Linear Evolution Recurrence) is an experimental sequence-model architecture exploring alternating complex-valued state-space modules and decoupled delta-memory blocks. The hypothesis is that evolving state and selective memory updates may serve different roles. Whether this combination improves the efficiency or quality of sequence modeling remains to be tested against controlled baselines.

EXPERIMENTAL RESEARCH / IN PROGRESS
STATE EVOLUTION / 002INPUT → UPDATE → NEXT STEP
Conceptual EILER architecture with alternating state-space and delta memory blocksINPUTxₜCOMPLEXSSMstate updateDELTAMEMORYselective writeOUTPUTyₜCARRY STATE FORWARDMEMORY FEEDS THE NEXT STEP
FIG. 01CONCEPTUAL BLOCK DIAGRAM
01 / THE RESEARCH QUESTIONSEQUENCE MODELING

What information should survive each step?

A sequence model needs a mechanism for turning past inputs into information that can influence later outputs. The design trade-off is between preserving detail, maintaining useful long-range signals, and keeping computation and memory manageable.

Attention mechanisms can directly compare positions across a context, while recurrent and state-space approaches propagate a compact state as inputs arrive. Compact state can make continued processing attractive, but compression may discard a detail that becomes important later. No single approach is best for every task or budget.

EILER explores a hybrid design: a complex-valued state-space path for evolving dynamics, alongside a separate delta-memory path for selective writes or revisions. The architecture adds complexity, so it earns its place only if ablations and baseline comparisons show a meaningful benefit.

RESEARCH HYPOTHESIS

Separating evolving state from explicit memory updates may make retention, compute cost, and information routing easier to inspect and compare.

02 / ARCHITECTUREALTERNATING MODULES

Two mechanisms. One testable hypothesis.

This diagram is a conceptual overview, not a full mathematical specification or evidence that the components outperform an alternative.

SEQUENCE INPUT
x₁x₂x₃…xₜ
01
Complex state-space moduleProcess the current input with a compact evolving state.
S(z)
↓ state representation
02
Decoupled delta-memory blockUse a separate update path to write or revise stored information.
ΔM
↓ combined representation
03
Next state-space moduleContinue processing with the updated representation.
S(z)
↓
OUTPUT REPRESENTATION
UPDATED INFORMATION CARRIES INTO THE NEXT TIME STEP
State evolution Selective memory updateConceptual, not to scale
03 / DESIGN RATIONALESEPARATION OF CONCERNS
A

Complex-valued state-space recurrence

The state-space path is intended to capture sequence dynamics in a compact evolving representation. Complex-valued parameterizations may be useful for some dynamics, but expressiveness in notation does not guarantee better learning. The parameterization, stability, optimization, and task all matter.

RecurrenceState dynamicsSequence processing
B

Decoupled delta memory

The delta-memory path provides a separate update route for a stored memory representation. The design questions include when writes occur, how new information interacts with existing contents, what gets overwritten, and how memory and runtime scale with the sequence and hidden dimensions.

Memory updatesGatingRetention
C

Alternation as an architectural hypothesis

Alternating components changes how information moves through the model and adds potential failure points: gradient flow, initialization, normalization, routing, and extra compute. The combination should be retained only if controlled ablations justify the added complexity.

CompositionOptimizationAblations
04 / HOW TO TEST THE IDEABASELINES BEFORE BIG CLAIMS

A plausible diagram is not evidence.

Architecture research requires matched conditions. EILER should be compared with credible reference models using the same data, tokenization, training budget, and evaluation protocol. Quality must be reported alongside parameters, memory, throughput, latency, convergence, and implementation cost.

EXPERIMENTQUESTION
Baseline comparisonDoes the hybrid outperform a well-tuned reference model?
Remove delta memoryWhat changes when explicit memory is ablated?
Remove complex stateIs the state-space component contributing measurable value?
Longer sequencesHow do quality, memory, and latency scale with context?
Multiple random seedsAre observed differences stable rather than noise?

This page does not claim a performance advantage. Results should be published only with enough detail to reproduce the training run, reconstruct the baseline, and understand both positive and negative outcomes.

05 / OPEN QUESTIONSTHE WORK AHEAD
MODEL DESIGN

Specify state and memory updates

Document tensor shapes, state transitions, write rules, initialization, normalization, gradient flow, and computational complexity.

EXPERIMENTS

Run controlled comparisons

Compare to well-tuned baselines; record loss, throughput, peak memory, convergence, generalization, and seed-to-seed variance.

ANALYSIS

Probe long-range information use

Use tasks with controlled dependencies and distractors to test whether remembered information changes the right output, not just whether loss decreases.

RESEARCH IN PROGRESS

The architecture is a hypothesis—not a result.

EILER is an experimental line of work. As implementations and results mature, this page should grow to include reproducible methods and findings.

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